The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device capable of masking an undesired column access signal.
FIG. 1A is a schematic circuit diagram showing a path to write data into a memory cell 150 and FIG. 1B is a timing chart for the circuit diagram of a prior art shown in FIG. 1A.
Conventionally, when a data masking signal reaches an active level, global input/output data lines GIO/GIOZ, which are inputted into a write driver 110, are masked. Namely, data, which are in global input/output data lines GIO/GIOZ, are not transmitted into local input/output data lines so that the data are not written in the memory cell 150. However, a column access signal Yi, which is a control signal selecting column lines, is not masked.
The column access signal Yi increases the voltage level of the bit line bar BLZ by transmitting the voltage of sub input/output lines SIO/SIOZ charged to an internal voltage level of Vintc bit lines BL/BLZ (NOT SHOWN). When the column access signal Yi disappears, the increased voltage level of the bit line bar BLZ returns to the original voltage level by the operation of a bit line sense amplifier 140. However, if a precharge command is applied before the increased voltage level of the bit line bar BLZ returns to the original voltage level, the third NMOS transistor NM3 is turned off because the voltage level of the word line WL becomes a low voltage level in the memory cell 150. At this time, since the capacitor in the memory cell 150 is still charged with the increased voltage level, an original data, xe2x80x980xe2x80x99, representing the discharged state of the capacitor, is lost. The bank write enable signal bwen inputted into the write driver 110 is a flag signal to enable the write of a bank. A block selection signal bs is a gate control signal to control the first NMOS transistor NM1 in the block selection unit 120.
A write signal and data are inputted into the write driver 110 through the global I/O lines with a bank write enable signal bwen. Then the data inputted through the global input/output data lines GI0/GI0Z are transmitted to local input/output data lines LI0/LI0Z. When the block selection signal bs is applied to the block selection unit 120, data is transmitted to the sub input/output lines SIO/SIOZ. When the column access signal Yi is applied to the column selection unit 130, data is transmitted through the bitline sense amplifier 140 and to the memory cell 150 selected by a wordline and a bitline. If the data is masked at this time, data is not written in the memory cell 150.
When the write data masking signal wdm is inputted into the write driver 110 to mask the data, in the global input/output lines GIO/GIOZ, data is not transmitted to the local input/output lines LIO/LIOZ. However, a dummy column access signal is generated because control signals, except data, are not masked. When the undesired column access signal is applied to a second NMOS transistor NM2 in the column selection unit 130, voltage of the sub input/output lines SIO/SIOZ, which is precharged to Vintc, is applied to the bitline bar blz so that the voltage level of the bitline bar blz increases. If a precharge command is applied and the word line transistor NM3 is turned off before the voltage level of the bitline bar blz returns to the original voltage level, the increased voltage is written in the memory cell 150 so that the data stored in the memory cell 150 is lost. Therefore, normal operation of the semiconductor memory device cannot be expected.
It is, therefore, an object of the present invention to provide a semiconductor memory device capable of masking a dummy column access signal by using a write data masking signal.
In accordance with an aspect of the present invention, there is provided a semiconductor memory device, comprising: a masking means for masking the generation of a column access signal by using a write data masking signal, wherein the masking means includes: a control signal generating means for receiving control signals including a write data masking signal, a column address signal and a read/write strobe signal and outputting a control signal to prevent the enabling of an undesired column access signal and a column address decoding means for outputting a column access signal in response to the control signal from the control signal generating means.